Repository Index

A FPGA friendly 32 bit RISC-V CPU implementation

• riscv
• soc
• cpu
• spinalhdl

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

• systemverilog-hdl
• cpu
• asic
• fpga