A FPGA friendly 32 bit RISC-V CPU implementation
- riscv
- soc
- cpu
- spinalhdl
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The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
- systemverilog-hdl
- cpu
- asic
- fpga
Raspberry Pi ARM based bare metal examples