OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Verilog Ethernet components for FPGA implementation
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Open source FPGA-based NIC and platform for in-network compute
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RTL, Cmodel, and testbench for NVDLA
Verilog AXI components for FPGA implementation
IC design and development should be faster,simpler and more reliable
Must-have verilog systemverilog modules
The Ultra-Low Power RISC-V Core
SERV - The SErial RISC-V CPU
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
RISC-V CPU Core (RV32IM)
Verilog PCI express components
A small, light weight, RISC CPU soft core
A Pi emulating a GameBoy sounds cheap. What about an FPGA?
CHIP-8 console on FPGA
Implementation Nintendo's GameBoy console on an FPGA
Game Boy Classic fully functional FPGA implementation from scratch