Repository Index

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

• opendb-database
• openroad
• lef
• verilog

Verilog Ethernet components for FPGA implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

• riscv
• verilog
• risc-v
• fpga

Verilog AXI components for FPGA implementation

IC design and development should be faster，simpler and more reliable

Must-have verilog systemverilog modules

• fpga
• delay
• debounce
• encoder

The Ultra-Low Power RISC-V Core

• risc-v
• riscv
• fpga
• hummingbird

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

RISC-V CPU Core (RV32IM)

• risc-v
• cpu
• verilog
• fpga

Verilog PCI express components