Repository Index

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

• opendb-database
• openroad
• lef
• verilog

IC design and development should be faster，simpler and more reliable

Must-have verilog systemverilog modules

• fpga
• delay
• debounce
• encoder

SERV - The SErial RISC-V CPU

• verilog
• fpga
• asic
• risc-v

RISC-V CPU Core (RV32IM)

• risc-v
• cpu
• verilog
• fpga

Game Boy Classic fully functional FPGA implementation from scratch