A minimal GPU design in Verilog to learn how GPUs work from the ground up
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Chisel: A Modern Hardware Design Language
- chisel
- chisel3
- scala
- firrtl
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
- systemverilog-hdl
- cpu
- asic
- fpga
Open-source E-ink monitor. Mirror of https://gitlab.com/zephray/glider
A machine learning accelerator core designed for energy-efficient AI at the edge.
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
- rocket-chip
- chip-generator
- chisel
- riscv
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
SonicBOOM: The Berkeley Out-of-Order Machine
- riscv
- boom
- chisel
- rtl
Scots Army Knife for electronics
RTL, Cmodel, and testbench for NVDLA
A modern hardware definition language and toolchain based on Python
- fpga
- hdl
- amaranth-hdl
Gameboy CPLD implementation of MBC5/MBC1 Hybrid
Game Boy Classic fully functional FPGA implementation from scratch
A systemVerilog implementation of Game Boy on DE1-SoC