Open-source high-performance RISC-V processor
- risc-v
- microarchitecture
- chisel
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Open-source high-performance RISC-V processor
Yosys Open SYnthesis Suite
Chisel: A Modern Hardware Design Language
Build your hardware, easily!
Rocket Chip Generator
A FPGA friendly 32 bit RISC-V CPU implementation
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Verilog Ethernet components for FPGA implementation
VHDL 2008/93/87 simulator
Open-source E-ink monitor. Mirror of https://gitlab.com/zephray/glider
A machine learning accelerator core designed for energy-efficient AI at the edge.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Open source FPGA-based NIC and platform for in-network compute
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
RTL, Cmodel, and testbench for NVDLA
Verilog AXI components for FPGA implementation
IC design and development should be faster,simpler and more reliable
Must-have verilog systemverilog modules
XLS: Accelerated HW Synthesis
:snowflake: Visual editor for open FPGA boards
Multi-platform nightly builds of open source digital design and verification tools
Universal utility for programming FPGA
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit