A FPGA friendly 32 bit RISC-V CPU implementation
- riscv
- soc
- cpu
- spinalhdl
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A FPGA friendly 32 bit RISC-V CPU implementation
Verilog Ethernet components for FPGA implementation
A machine learning accelerator core designed for energy-efficient AI at the edge.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Verilog AXI components for FPGA implementation
Implementation Nintendo's GameBoy console on an FPGA
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Game Boy Classic fully functional FPGA implementation from scratch
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