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A FPGA friendly 32 bit RISC-V CPU implementation
- riscv
- soc
- cpu
- spinalhdl
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
- systemverilog-hdl
- cpu
- asic
- fpga
Verilog Ethernet components for FPGA implementation
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Open source FPGA-based NIC and platform for in-network compute
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Scots Army Knife for electronics
GPGPU microprocessor architecture
Machine learning on FPGAs using HLS
- hls
- machine-learning
- fpga
- python
Verilog AXI components for FPGA implementation
A modern hardware definition language and toolchain based on Python
- fpga
- hdl
- amaranth-hdl
Dataflow compiler for QNN inference on FPGAs
A Pi emulating a GameBoy sounds cheap. What about an FPGA?
hBPF = eBPF in hardware
CHIP-8 console on FPGA
Implementation Nintendo's GameBoy console on an FPGA
Gameboy CPLD implementation of MBC5/MBC1 Hybrid
Game Boy Classic fully functional FPGA implementation from scratch
A systemVerilog implementation of Game Boy on DE1-SoC