Repository Index

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

• systemverilog-hdl
• cpu
• asic
• fpga

cocotb: Python-based chip (RTL) verification

• python
• vhdl
• verilog
• uvm

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

• hardware
• cpucore
• risc-v
• rv32

RISC-V CPU Core (RV32IM)

• risc-v
• cpu
• verilog
• fpga

Multi-platform nightly builds of open source digital design and verification tools

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

• axi
• axi4
• axi4-lite
• systemverilog