A minimal GPU design in Verilog to learn how GPUs work from the ground up
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Chisel: A Modern Hardware Design Language
- chisel
- chisel3
- scala
- firrtl
Build your hardware, easily!
A FPGA friendly 32 bit RISC-V CPU implementation
- riscv
- soc
- cpu
- spinalhdl
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
- systemverilog-hdl
- cpu
- asic
- fpga
Verilog Ethernet components for FPGA implementation
VHDL 2008/93/87 simulator
- vhdl
- ghdl
- simulator
- testbench
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
cocotb: Python-based chip (RTL) verification
Open source FPGA-based NIC and platform for in-network compute
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
- rocket-chip
- chip-generator
- chisel
- riscv
The repository host gives no description.
Python Productivity for ZYNQ
- pynq
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Circuit IR Compilers and Tools
- circt
- llvm
- mlir
GPGPU microprocessor architecture
RTL, Cmodel, and testbench for NVDLA
Verilog AXI components for FPGA implementation
Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)
HDL libraries and projects
- analog-devices
- hdl
- jesd204b
- verilog
Scala based HDL
IC design and development should be faster，simpler and more reliable
Must-have verilog systemverilog modules
- fpga
- delay
- debounce
- encoder
The Ultra-Low Power RISC-V Core