A minimal GPU design in Verilog to learn how GPUs work from the ground up
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The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
- systemverilog-hdl
- cpu
- asic
- fpga
Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)
Must-have verilog systemverilog modules
- fpga
- delay
- debounce
- encoder
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
- axi
- axi4
- axi4-lite
- systemverilog
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
Haskell to VHDL/Verilog/SystemVerilog compiler
A Verilog synthesis flow for Minecraft redstone circuits
A systemVerilog implementation of Game Boy on DE1-SoC