A minimal GPU design in Verilog to learn how GPUs work from the ground up
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Yosys Open SYnthesis Suite
Chisel: A Modern Hardware Design Language
- chisel
- chisel3
- scala
- firrtl
Build your hardware, easily!
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
- systemverilog-hdl
- cpu
- asic
- fpga
VHDL 2008/93/87 simulator
- vhdl
- ghdl
- simulator
- testbench
A machine learning accelerator core designed for energy-efficient AI at the edge.
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
- rocket-chip
- chip-generator
- chisel
- riscv
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Machine learning on FPGAs using HLS
- hls
- machine-learning
- fpga
- python
HDL libraries and projects
- analog-devices
- hdl
- jesd204b
- verilog
IC design and development should be faster，simpler and more reliable
Must-have verilog systemverilog modules
- fpga
- delay
- debounce
- encoder
XLS: Accelerated HW Synthesis
SERV - The SErial RISC-V CPU
RISC-V CPU Core (RV32IM)
Multi-platform nightly builds of open source digital design and verification tools
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
- axi
- axi4
- axi4-lite
- systemverilog
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
Haskell to VHDL/Verilog/SystemVerilog compiler
A Verilog synthesis flow for Minecraft redstone circuits
A very simple and easy to understand RISC-V core.
RISC-V SoC designed by students in UCAS
Image Signal Processor
- isp
- image-processing
- image-signal-processor