A FPGA friendly 32 bit RISC-V CPU implementation
- riscv
- soc
- cpu
- spinalhdl
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A FPGA friendly 32 bit RISC-V CPU implementation
An environmental monitoring and regulation system
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
A privacy-first, open-source home assistant
Universal grid map library for mobile robotic mapping
OpenCalib: A Multi-sensor Calibration Toolbox for Autonomous Driving
[CVPR 2025] MASt3R-SLAM: Real-Time Dense SLAM with 3D Reconstruction Priors
Dexbotic: Open-Source Vision-Language-Action Toolbox
[IROS 2025 Best Paper Award Finalist & IEEE TRO 2026] The Large-scale Manipulation Platform for Scalable and Intelligent Embodied Systems
The new generation chameleon based on NRF52840 makes the performance of card emulation more stable. And gave the chameleon the ability to read, write, and decrypt cards.
A serial device I/O tool
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
An open source platform for visual-inertial navigation research.
Embedded Template Library
Exploring possibilities of ESP32 platform to attack on nearby Wi-Fi networks.
Verilog Ethernet components for FPGA implementation
High-performance C++ library for multiphysics and multibody dynamics simulations
Implementations of SIMD instruction sets for systems which don't natively support them.
Open source, local, and self-hosted Amazon Echo/Google Home competitive Voice Assistant alternative
A functional tools for z*e devices (F50 | U30 Air)
Tiny, fast, non-dependent and fully loaded printf implementation for embedded systems. Extensive test suite passing.
Home automation firmware for ESP8266-based devices
A free open source IT asset / Equipment / management and scheduling system.
This revolutionary software enables EV battery packs to be easily reused for stationary storage in combination with solar inverters